Field of the Invention
Embodiments of the present invention relate generally to graphics processing and, more specifically, to techniques for limiting power via secondary control of a voltage regulator.
Description of the Related Art
Computer systems performing data processing, in particular graphics processing, include millions of integrated transistors and transistor pairs that actively switch between a supply voltage level and a ground, or zero voltage, reference level during operation. As the number of cells that actively switch during operation increases, the overall power consumption of the system increases. Furthermore, the frequency at which the cells actively switch contributes to power consumption, because power usage increases as cells switch faster.
A computer subsystem receives power from a power supply. A power supply typically includes a regulator that provides a fixed voltage. The regulator must be specified to provide a maximum power, that is, the fixed voltage at some maximum current. Frequently, the processing demands of a computer subsystem create a wide range of dynamic load on the regulator. The system performance metrics may be related to the average of the dynamic loading, but the power supply must be designed to handle the peak of the load.
The above condition may be avoided by careful design to limit/match the total processing power to the capability of the power supply. Such an approach may lead to an overdesigned power supply, with the associated size and weight penalties. Alternatively, the processing frequency may be reduced to limit/match the peak power usage to the capability of the power supply. Such an approach imposes a constraint on the performance of the subsystem by limiting processing speed.
As an alternative to trying to limit/match total processing power to the capability of the power supply, some computer systems measure power consumption via voltage and current measurements and reduce processing speed to cap the power consumption below a maximum power limit. Such an approach can act to compress the dynamic range of the loading power to increase the average loading while limiting the peak power below a specified limit.
One drawback to implementing a clock based power limit is that a digital processor must understand its power consumption through an analog to digital conversion of a sensor, or by a computation of power based on its activity. This analog to digital conversion or activity computation can cause delays that may preclude the system from responding to a given load increase before the power supply exceeds its specified limit. These conversion delays are compounded further by communication delays over I2C or other interface between the processor and the sensor. In short, the clock based response may not be fast enough to preclude the system load from exceeding the capability of the power supply. Further, a step decrease in frequency may not adequately coordinate the processing demands of the system with capability of the power supply. When a step reduction in frequency occurs, the power usage is reduced. The resulting power usage may be significantly less than the capability of the power supply, resulting in underutilization of system resources.
As the foregoing illustrates, what is needed in the art are more effective ways to limit power consumption when the processing demands of a system change.